1. Field of the Invention
The present invention relates to an information processing device comprising a plurality of CPUs, and more particularly, to an information processing device which immediately executes an interrupt condition change instruction if no pending floating interrupt as an interrupt that can be executed by any of the plurality of CPUs exists.
2. Description of the Related Art
In an information processing device comprising a plurality of CPUs, there are various methods in the case where one or the plurality of CPUs are made to execute interrupt processing. For example, the case where a particular CPU is specified and made to execute interrupt processing, the case of a broadcast interrupt that makes all of the CPUs execute interrupt processing, the case of a floating interrupt (an event-like interrupt) that may make any of the plurality of CPUs execute interrupt processing, or the like. The present invention targets an information processing device which makes the above described floating interrupt pending.
Normally, interrupt processing is not immediately executed in all cases, and its execution is sometimes made pending. Assume that one of a plurality of CPUs decodes an interrupt condition change instruction within a program, and this instruction is attempted to be executed. This interrupt condition change instruction is, for example, an instruction which changes an interrupt enable mask to be described later.
Normally, when this interrupt condition change instruction is executed, whether or not an interrupt to be processed under a current interrupt condition is pending is examined within an information processing device. If the interrupt to be processed is pending, this instruction is executed after the interrupt processing is executed. If the interrupt to be processed is not pending, the instruction is immediately executed.
A conventional method for processing such a pending floating interrupt will be described below by taking an input/output interrupt as an example of a floating interrupt. FIG. 1 is a block diagram showing the fundamental configuration of an information processing device for an explanation of pending input/output interrupt processing. In this figure, the information processing device comprises an IOP (Input/Output Processor) 50, an MCU (Memory Control Unit) controlling a storage device such as a main storage, etc., and a plurality of CPUs (Central Processing Units) 520 to 52n. The CPUs 520 to 52n respectively include instruction controlling units 530 to 53n controlling instructions within the respective CPUs.
In FIG. 1, an input/output interrupt, for example, an interrupt corresponding to each of a plurality of input/output channels is transmitted from the IOP 50 to the MCU 51 as a floating interrupt, for example, along with the signal indicating that the interrupt is pending. Within the MCU 51, data indicating whether or not a floating interrupt is pending is stored in correspondence with each of the channels in a pending latch to be described later.
An interrupt condition change instruction changing an interrupt condition is decoded, for example, by one of the plurality of CPUs 520 to 52n, and the need for executing this instruction arises. A floating interrupt may be executed by any of the CPUs as described above. Therefore, each of the instruction controlling units 530 to 53n within each of the CPUs transmits to the MCU 51 an interrupt enable mask stored therein, that is, the value of the mask indicating whether or not an interrupt is enabled for its CPU in correspondence with each of the input/output channels.
Since the interrupt enable mask and the above described pending latch store the data corresponding to each of the channels one by one, the MCU transmits an interrupt processing request signal (trigger signal) to the instruction controlling unit within the CPU whose mask value of the input/output channel corresponding to the pending interrupt is, for example, 1, and whose priority is the highest. The CPU controlled by the instruction controlling unit starts the interrupt processing upon receipt of the trigger signal.
FIG. 2 is a flowchart showing a conventional interrupt condition change instruction process. Once the process is started in this figure, an interrupt condition change instruction is first decoded, for example, by a certain CPU in step S10 and the need for executing this instruction arises. Then, an interrupt enable mask is transmitted from the instruction controlling unit in each of the CPUs to the MCU in step S11. If a pending floating interrupt exists, the process for selecting a CPU made to execute this interrupt and for transmitting a trigger signal to the selected CPU is started prior to the execution of the interrupt condition change instruction on the MCU side.
In the instruction controlling unit in each of the CPUs, a counter, for example, a process wait counter to be described later, is started in order to wait for a trigger signal which can possibly be transmitted from the MCU side, when the interrupt enable mask is transmitted in step S11, and whether or not the counter times out is determined in step S12. If the counter does not time out, whether or not the trigger signal is reached is determined in step S13. If the trigger signal is not reached, the operations in and after step S12 are repeated.
If the trigger signal is determined to be reached in step S13 before the counter does not time out in step S12, the pending interrupt is processed by the CPU which has received the trigger signal, that is, the selected CPU. In the unselected CPUs, the interrupt condition change instruction in step S15 is executed when the counter is determined to time out in step S12, and, for example, the interrupt enable mask stored in the instruction controlling unit is rewritten.
FIG. 3 is a block diagram showing the configuration of the information processing device in which the configuration of the MCU is especially illustrated in detail. Processing for a pending floating interrupt in this figure will be explained below. In this figure, an IO rupture (RUPT) ID (7 bits+parity check bit P) signal (+IO_RUPT_ID) indicating to which one of for example, 128 input/output channels an interrupt corresponds is transmitted from the IOP 50 to the MCU 51 along with a signal (+SET_PENDING) making an IO (Input/Output) interrupt pending in (1). These values are once stored in a 10-bit latch 70. Then, the value of the IO rupture ID by a decoder 71, and the bit corresponding to the input/output channel for which an interrupt is made pending is assumed to be xe2x80x9c1xe2x80x9d among four pending latches 721 to 724 of 32 bits respectively corresponding to the 128 channels in (2).
When one CPU decodes an interrupt condition change instruction and the need for executing the decoded instruction arises, the contents (128 bits) of the IO rupture masks 790 to 7915 indicating whether or not an interrupt corresponding to the respective input/output channels is enabled are serially transferred, for example, by 4 bits in 32 time divisions by the instruction controlling unit within each of the CPUs. This serial transfer is not limited particularly to 32 time divisions.
A priority circuit 75, which selects the CPU made to process a pending floating interrupt as described above within the MCU 51, makes a comparison between the interrupt enable mask transmitted from the CPU side and the contents stored in the pending latches, and determines whether or not an interrupt by each of the CPUs is enabled for the pending floating interrupt. Accordingly, the contents stored in the respective pending latches 721 to 724 are serially transferred to the priority circuit 75 via selectors 731 to 734 according to the selection control of a mask select counter. Here, the mask select counter is a counter for this time division transfer, and does not always mean a mask selection.
The priority circuit 75 makes a comparison between the contents stored in the pending latches and the interrupt enable mask transmitted from the CPU side, and selects the CPU which is in a wait state and physically has a smaller component number under the same condition from among CPUs for which an interrupt is enabled as a CPU made to process a pending interrupt. Here, the information of the CPU in the wait state is provided to the priority circuit 75 as a CPU wait state in signal (CPU_WAIT_STATE_IN) in (5).
The priority circuit 75 provides a trigger signal (IO_RUPT_TGR) and an IO rupture ID signal (IO_RUPT_ID) (8 bits including a parity check bit P) corresponding to an input/output channel number to one of latches 760 to 7615 which correspond to the CPUs 520 to 5215 one by one. Its contents are transmitted to the CPU side via any of latches 770 to 7715 by the selection control of the mask select counter, for example, by using a serial transfer in 16 time divisions according to the selection control of a mask selection counter in (6). The transmitted signal is stored in any of latches 780 to 7815 within the instruction controlling unit on the CPU side, and used to process the pending interrupt.
Upon completion of the interrupt process on the CPU side, a reset rupture pending signal (RESET_RUPT_PENDING) and a reset rupture trigger signal (RESET_RUPT_TRG) are serially transferred to the MCU 51, for example, in 16 time divisions as a cancel signal (CPU_IO_RUPT_CNTL_IN) in (7), and the corresponding bits within the pending latches 721 to 724 and within the latches 760 to 7615 corresponding to the respective CPUs are reset.
As described above, with the conventional pending interrupt processing method, a trigger signal transmitted from the MCU side must be waited to determine whether or not there is an interrupt to be processed by a corresponding CPU after the instruction controlling unit in each CPU transmits an interrupt enable mask to the MCU side. Since the MCU side transmits a trigger signal only to the CPU made to process the pending interrupt, even the CPUs which are not required to execute the pending interrupt must wait until a counter times out as explained in step S12.
In the first place, even if no pending floating interrupts exist on the MCU side, all of the CPUs cannot execute an interrupt condition change instruction until a timer times out. That is, each CPU spends a useless wait time, for example, whenever an instruction rewriting an interrupt enable mask is decoded on the CPU side, which leads to a performance degradation of an information processing device.
An object of the present invention is to speed up the processing for an interrupt condition change instruction by eliminating the need for spending a useless wait time if no pending floating interrupts exist or if no pending interrupt to be executed by a corresponding CPU exists, in an information processing device which comprises a plurality of CPUs, inquires of an MCU as to whether or not a floating interrupt which can be executed by any of the plurality of CPUs is pending, when a certain CPU decodes an interrupt condition change instruction, and executes the interrupt condition change instruction when there is no instruction for a pending floating interrupt to the corresponding CPU.
An information processing device according to the present invention comprises a plurality of CPUs, and can make a floating interrupt as an interrupt which can be executed by any of the plurality of CPUs pending. This information processing device comprises an interrupt pending signal generating unit which always transmits a signal indicating the presence/absence of a pending floating interrupt to the plurality of CPUs; and an interrupt condition change instruction execution controlling unit which is comprised by each of the CPUS, and immediately makes its own CPU execute an interrupt condition change instruction when the interrupt condition change instruction is issued and the output of the interrupt pending signal generating unit indicates the absence of a pending interrupt.
With such a configuration, a CPU can immediately execute an interrupt condition change instruction on the condition that no pending floating interrupts exist when the interrupt condition change instruction is issued, thereby improving the performance of the information processing device.